1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to to semiconductor workpieces or wafers and to methods of application backside metallizations to the same.
2. Description of the Related Art
Conventional semiconductor chips or dies are routinely fabricated en masse in large groups as part of a single semiconductor wafer. At the conclusion of the processing steps to form the individual dies, a so-called dicing or sawing operation is performed on the wafer to cut out the individual dies. Thereafter, the dies may be packaged or directly mounted to a printed circuit board of one form or another.
A typical conventional semiconductor wafer is manufactured with scores or more dies. This fabrication process consists of a large number of manufacturing steps, such as photolithography, ion implants, anneals, etches, chemical and physical vapor deposition and plating to name a few. Significant effort is expended by semiconductor manufacturers toward the goal of achieving nearly identical manufacturing outcomes for the individual semiconductor dies of a wafer. However, inevitable variations in the multitude of processing steps to build the dies leads to performance differences between some or all of the dies of a given wafer. For example, some of dies of a wafer will have relatively higher native clock speeds and power dissipation and some will have lower native clock speeds and power dissipation.
Many types of semiconductor dies dissipate sufficient levels of power such that appropriate thermal management calls for the usage of solder-type thermal interface materials (TIMs) to convey heat from the die to a heat spreader, such as a lid. Silicon typically does not exhibit favorable solder wettable properties. Accordingly, such semiconductor chips, and the wafers that spawn them, frequently include backside structure that may be a unitary or laminate structure of materials that provide a solder wettable interface between the semiconductor chip and the solder-type TIM.
One conventional backside metallization technique involves dedicating a given wafer to a particular application, i.e., to high power parts for use with a lid. The wafer is blanket coated with the backside metallization. However, it may turn out that some of the dies of the wafer ultimately clock out lower than expected in which case the slower dies might be better suited for lidless applications or applications that use organic TIMs. Each of those applications is incompatible with backside metallization. Likewise, there may be current market conditions that favor usage of dies in lidless applications over high power lidded applications. Since the wafer in question has been built with blanket backside metallization, there is no flexibility to go with lidless or organic TIM applications for the slower, lower power dies.
Another conventional wafer fab technique to deal with lidless or organic TIM applications is to fabricate a wafer without any backside metallization. Those dies that natively clock out high and operate with high power consumption are incompatible with solder-type TIMs and so must be used in low power and/or organic TIM applications and possibly with deliberate under clocking.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.